a = 5;
b = 10;

class Ab {
  public int a;
  public int b;
}

void thread1(Ab ab) {
  ab.a = 5;
  ab.b = 10;
}

void thread2(Ab ab) {
  if (ab.a != 5 && ab.b == 10) {
    impossible();
  }
}

            while (1 == Interlocked.CompareExchange(ref m_dwBusy, 1, 0))
            {
                //здесь должна быть pause
            }

A read of a volatile field is called a volatile read. A volatile read has “acquire semantics”; that is, it is guaranteed to occur prior to any references to memory that occur after it in the instruction sequence.
A write of a volatile field is called a volatile write. A volatile write has “release semantics”; that is, it is guaranteed to happen after any memory references prior to the write instruction in the instruction sequence.

void Foo(){
Thread.MemoryBarrier();
}

 #elif defined(HOST_X86)

  #define YieldProcessor() __asm { rep nop }
  #define MemoryBarrier() MemoryBarrierImpl()
  __forceinline void MemoryBarrierImpl()
  {
      int32_t Barrier;
      __asm {
          xchg Barrier, eax
      }
  }

Ф>void Foo(){
Ф>Thread.MemoryBarrier();
Ф>}
Ф>

:-)

8.2.2 Memory Ordering in P6 and More Recent Processor Families

...
Reads or writes cannot be reordered with I/O instructions, locked instructions, or serializing instructions.
...
Locked instructions have a total order.

11.10 STORE BUFFER

Intel 64 and IA-32 processors temporarily store each write (store) to memory in a store buffer. The store buffer
improves processor performance by allowing the processor to continue executing instructions without having to
wait until a write to memory and/or to a cache is complete. It also allows writes to be delayed for more efficient use
of memory-access bus cycles.

In general, the existence of the store buffer is transparent to software, even in systems that use multiple processors.
The processor ensures that write operations are always carried out in program order. It also insures that the
contents of the store buffer are always drained to memory in the following situations:

...

* When a LOCK operation is performed.

...

22.34 STORE BUFFERS AND MEMORY ORDERING

The Pentium 4, Intel Xeon, and P6 family processors provide a store buffer for temporary storage of writes (stores)
to memory (see Section 11.10, “Store Buffer”). Writes stored in the store buffer(s) are always written to memory
in program order, with the exception of “fast string” store operations (see Section 8.2.4, “Fast-String Operation and
Out-of-Order Stores”).

The Pentium processor has two store buffers, one corresponding to each of the pipelines. Writes in these buffers
are always written to memory in the order they were generated by the processor core.

It should be noted that only memory writes are buffered and I/O writes are not. The Pentium 4, Intel Xeon, P6
family, Pentium, and Intel486 processors do not synchronize the completion of memory writes on the bus and
instruction execution after a write. An I/O, locked, or serializing instruction needs to be executed to synchronize
writes with the next instruction (see Section 8.3, “Serializing Instructions”).

#include <atomic>
#include <cstdio>
#include <thread>
 
int data;
std::atomic<bool> ready;
 
void producer()
{
    data = 123;
    ready.store(true, std::memory_order_release);
}
 
void consumer()
{
    while (false == ready.load(std::memory_order_acquire)) {}
    printf("data = %d", data);
}
 
int main()
{
    std::thread t1(producer);
    std::thread t2(consumer);
    t1.join(); t2.join();
    return 0;
}

void producer(void) PROC
    mov     DWORD PTR int data, 123
    npad    1
    mov     BYTE PTR std::atomic<bool> ready, 1
    ret     0
void producer(void) ENDP 

void consumer(void) PROC
    npad    2
$LL2@consumer:
    movzx   eax, BYTE PTR std::atomic<bool> ready
    npad    1
    test    al, al
    je      SHORT $LL2@consumer
    ...
void consumer(void) ENDP